Patent Application 17936393 - VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH

Title: VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH SHARED BACKSIDE POWER SUPPLY

Application Information

Invention Title: VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH SHARED BACKSIDE POWER SUPPLY
Application Number: 17936393
Submission Date: 2025-05-20T00:00:00.000Z
Effective Filing Date: 2022-09-29T00:00:00.000Z
Filing Date: 2022-09-29T00:00:00.000Z
National Class: 257
National Sub-Class: 329000
Examiner Employee Number: 90001
Art Unit: 2817
Tech Center: 2800

Rejection Summary

102 Rejections: 2
103 Rejections: 2

Cited Patents

No patents were cited in this rejection.

Office Action Text

DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.

Claims 1-2, 5-6 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Do (US 20200144260 A1, hereinafter Do‘260).

Regarding independent claim 1, Do‘260 teaches, “A semiconductor device (fig. 29-30; ¶¶ 0040-0108) comprising:
a first vertical-transport field-effect transistor (VTFET) (P-type VFET on left side in fig. 30) on a wafer (100);
a second VTFET (N-type VFET on right side in fig. 30) adjacent to the first VTFET on the wafer (100);
a backside power delivery network (102_P and 102_N) on a backside of the wafer (100);
a shared frontside contact (44_O), wherein the shared frontside contact (44_O) is on a frontside of the wafer (100); and
wherein the shared frontside contact (44_O) is connected (indirect contact) to a first top source/drain region (32_P) of the first VTFET, a second top source/drain region (32_N) of the second VTFET, and the backside power delivery network (102_P, 102_N)”.
The term "indirect contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected with one or more intermediary conducting, insulating or semiconductor layers at the interface of the two elements. In the instant case, element 44_O is indirectly connected to elements 102_P or 102_N with intermediatory layers 42_P, 32_P, 14_P, 12_P, 104_P or 42_N, 32_N, 14_N, 12_N, 104_N at the interface of these two elements.
The term "direct contact," or the like, means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

Regarding independent claim 6, Do‘260 teaches, “A semiconductor device (fig. 29-30; ¶¶ 0040-0108) comprising:
a plurality of vertical-transport field-effect transistors (VTFET) (a P-type VFET on left side and an N-type VFET on right side in fig. 30) on the semiconductor device;
a backside power delivery network (102_P and 102_N) on a backside of the semiconductor device,
wherein the backside power delivery network (102_P and 102_N) is connected to a source/drain region (12_P, 12_N) on the backside of at least one of the plurality of VTFET; and
a contact (44_O) on a frontside of the semiconductor device, wherein the contact (44_O) is connected (indirect contact) to the backside power delivery network (102_P and 102_N) and a top plurality of source/drain regions (16_P, 16_N) of the plurality of VTFET”.
The term "indirect contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected with one or more intermediary conducting, insulating or semiconductor layers at the interface of the two elements. In the instant case, element 44_O is indirectly connected to elements 102_P or 102_N with intermediatory layers 42_P, 32_P, 14_P, 12_P, 104_P or 42_N, 32_N, 14_N, 12_N, 104_N at the interface of these two elements.
The term "direct contact," or the like, means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

Regarding claim 2, Do‘260 further teaches “The semiconductor device of claim 1, wherein the first VTFET and the second VTFET are in parallel (fig. 30)”.

Regarding claim 5 and 12, Do‘260 further teaches “wherein the backside power delivery network (102_P, 102_N) is selected from the group consisting of power or ground (power)”.

Claims 15, 17-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sobue (US 20210082902 A1, hereinafter Sobue‘902).

Regarding independent claim 15, Sobue‘902 teaches, “A semiconductor device (fig. 7-12; ¶¶ 0049-0112) comprising:
a first vertical-transport field-effect transistor (VTFET) (right-hand g11 in fig.12) on a wafer (100);
a second VTFET (left-hand g11 in fig.12) adjacent to the first VTFET on the wafer (100);
a third VTFET (left-hand g21 in fig.12) adjacent to the first VTFET on the wafer;
wherein the first VIFET, the second VTFET, and the third VTFET are each a first width, wherein the width is a contacted poly pitch (CPP) (‘grid lines’, ¶ 0070); and
a shared frontside contact (131) connected to the first VTFET, second VTFET, and third VTFET, wherein the shared frontside contact (131) is on a frontside of the wafer (100)”.

Regarding claim 17, Sobue‘902 further teaches, “The semiconductor device of claim 15, wherein the shared frontside contact (131, fig. 12; ¶ 0101) is connected to a first top source/drain region of first VTFET, a second top source/drain region of the second VTFET and a third bottom source/drain region of the third VTFET”.

Regarding claim 18, Sobue‘902 further teaches, “The semiconductor device of claim 15, wherein the shared frontside contact (131, fig. 12; ¶ 0101) is connected to a first top source/drain region of first VTFET, a second bottom source/drain region of the second VTFET and a third top source/drain region of the third VTFET”.

Regarding claim 20, Sobue‘902 further teaches, “The semiconductor device of claim 15, wherein the first VTFET, second VTFET, and third VTFET are in parallel” (¶ 0093).

Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.

Claims 3-4, 7-11 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Do‘260 as applied to claim 1 as above, and further in view of Sobue‘902.

Regarding claim 3, Do‘260 teaches all the limitations described in claim 1.
But Do‘260 is silent upon the provision of wherein the first VTFET and the second VTFET are each a first width, wherein the first width is a contacted poly pitch (CPP), and wherein shared frontside contact is adjacent to the second VTFET by the first width.
However, Sobue‘902 teaches a vertical contact (e.g. via 28a in fig.6 or 228a,b in fig.24,30) connects the frontside shared contact (32 in fig.6 or 231 /232 in fig.24, 30) to the bottom source/drain region of the VTFETs (12 in fig.6 or 211 /212 in fig.24,30). The vertical contact (28a, 228a,b) of Sobue‘902 is also centered at approximately 1 CPP from the center of the adjacent VTFET, as clearly indicated by the grid lines in fig.6,24,30 (see also ¶ 0070 defining the "grid spacing" as the spacing used for placing the components at the time of designing, i.e. a pre-determined pitch, which is considered analogous to the CPP mentioned in the claim.
Do‘260 and Sobue‘902 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Do‘260 with the features of Sobue‘902 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Do‘260 and Sobue‘902 to arrange the VTFETs and the shared frontside contact according to the teachings of Sobue‘902 with a motivation of achieving high breakdown voltage and reducing off current. See Sobue‘902, ¶¶ 0002-0006.

Regarding claim 4, Do‘260 and Sobue‘902 further teach, “The semiconductor device of claim 1, further comprising: a bottom source/drain region of a third FET (g21), wherein the bottom source/drain region (12) is connected to the shared frontside contact (131, fig. 6, Sobue‘902)”.
Regarding claim 7, Do‘260 and Sobue‘902 further teach, “The semiconductor device of claim 6, wherein a first group of VTFET of the plurality of VTFET (E11 and E12 in the layout of fig.3 of Sobue‘902) are horizontally adjacent to a second group of VTFET of the plurality of VTFET”.

Regarding claim 8, Do‘260 and Sobue‘902 further teach, “The semiconductor device of claim 7, wherein a third group of VTFET (transistors with the second uppermost row of E11 in fig.3 of Sobue‘902) of the plurality of VTFET are vertically adjacent the first group of VTFET and second group of VTFET”.

Regarding claim 9, Do‘260 and Sobue‘902 further teach, “The semiconductor device of claim 6, wherein a first group of VTFET (transistors with the first uppermost row of E11 in fig.3 of Sobue‘902) of the plurality of VTFET are vertically adjacent to a second group of VTFET (transistors with the second uppermost row of E11 in fig.3 of Sobue‘902) of the plurality of VTFET”.

Regarding claim 10, Do‘260 and Sobue‘902 further teach, “The semiconductor device of claim 7, wherein a third group of VTFET (E13 in the layout of fig.3 of Sobue‘902) of the plurality of VTFET are horizontally adjacent the first group of VTFET and second group of VTFET”.

Regarding claim 11, Do‘260 and Sobue‘902 further teach, “The semiconductor device of claim 6, wherein at least a portion of the plurality of VTFET have a shared active area (12_M) connected to the contact (44_O, fig. 15A-15B, Do‘260)”.

Regarding claim 13, Do‘260 and Sobue‘902 further teach, “The semiconductor device of claim 8, wherein the third group of VTFET are in series (fig.3 of Sobue‘902)”.

Regarding claim 14, Do‘260 and Sobue‘902 further teach, “The semiconductor device of claim 8, wherein the third group of VTFET are in parallel (fig.3 of Sobue‘902)”.

Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sobue‘902 as applied to claim 15 as above, and further in view of Do (US 20200144418 A1, hereinafter Do‘418).

Regarding claim 16, Sobue‘902 teaches all the limitations described in claim 15.
But Sobue‘902 is silent upon the provision of wherein the shared frontside contact is horizontally adjacent to the first VTFET and second VTFET by the first width and wherein the shared frontside contact is vertically adjacent to the third VTFET by the first width.
However, Do‘418 teaches a similar VFETs (fig. 11-12), wherein the shared frontside contact (32/32_1c) is horizontally adjacent to the first VTFET (right-hand 16_P1 in fig.11B) and second VTFET (right-hand 16_N1 in fig.11B) by the first width (a distance that is equal to the pitch between the transistors i.e., first width = CPP along direction X) and wherein the shared frontside contact is vertically adjacent to the third VTFET by the first width (another portion of the shared frontside contact 32/32_1c (the one overlapping the right-hand 16_P1 in fig.11 B) is adjacent to the third VTFET (left-hand 16_P1 in fig.11 B) by the same distance).
Sobue‘902 and Do‘418 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Sobue‘902 with the features of Do‘418 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Sobue‘902 and Do‘418 to arrange the VTFETs and the shared frontside contact according to the teachings of Do‘418 with a motivation of exploiting high scalability and simpler interconnections between VFETs. See Do‘418, ¶¶ 0002-0004.

Regarding claim 19, Sobue‘902 and Do‘418 further teach, “The semiconductor device of claim 15, wherein the shared frontside contact (32, the straight portion parallel to the x axis in fig.11 B) is a second width, wherein the second width is double the first width (pitch between the transistor)”.

Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty and can also be used to reject the claims 1-20. Applicant is requested to review those prior arts to overcome the future rejection using these arts.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.

Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817